(1) Field of the Invention
The present invention relates to a packet transfer device and a semiconductor device, and more particularly to a packet transfer device, a semiconductor device, and a packet transfer system for transferring packets inputted from a plurality of input/output ports to corresponding input/output ports.
(2) Description of the Related Art
The growing popularity among many people of the Internet in recent years had led to the increasing use of access routers in home and SOHO (Small Office Home Office) environments.
Access routers that are mainly used at present are called “ISDN (Integrated Service Digital Network) router”. Generally, access routers have an interface having a frequency band of 64 Kbps for the WAN (Wide Area Network) side for accessing the Internet and a plurality of Ethernet interfaces having a frequency band of 10 Mbps for the home or SOHO side.
Communication services called broadband services including CATV (Cable Television), ADSL (Asymmetric Digital Subscriber Line), and FTTH (Fiber to The Home) have been emerged in recent years. These services have a WAN frequency band of 1 Mbps or higher, and some of them even have a side WAN frequency band of 100 Mbps. There is a possibility that there will be a demand for home or SOHO frequency bands in the range of 100 Mbps to meet the need for receiving and transmitting multimedia data.
FIG. 28 of the accompanying drawings shows a conventional access router by way of example.
As shown in FIG. 28, the conventional access router comprises a layer 2 (data link layer) switch 10 and a CPU (Central Processing Unit) 20.
The layer 2 switch 10 comprises a plurality of input/output ports 11 through 13, a plurality of MAC (Media Access Control) blocks (referred to as “processing circuits”) 14 through 16, a switch block 17, and a reference block 18.
The input/output ports 11 through 13 are connected to a WAN or a host for transmitting information thereto and receiving information therefrom.
The processing circuits 14 through 16 extract destination MAC addresses from packets that have been received by the input/output ports 11 through 13, supply the extracted destination MAC addresses to the reference block 18, and identify input/output ports from which to output data. The processing circuits 14 through 16 then supply the packets to the switch block 17 and output the packets from the identified input/output ports.
FIG. 29(A) of the accompanying drawings shows a detail structure of the processing circuit 14. As shown in FIG. 29(A), the processing circuit 14 comprises a reference block interface 14a, a switch block interface 14b, and a header information extractor 14c. 
The reference block interface 14a is an interface for connection to the reference block 18.
The switch block interface 14b is an interface for connection to the switch block 17.
The header information extractor 14c is a circuit for extracting header information (destination MAC address) from a packet.
Since the processing circuits 14 through 16 are structurally identical to each other, the processing circuits 15, 16 will not be described in detail below.
In FIG. 28, the reference block 18 identifies input/output ports from which to output data based on destination MAC addresses supplied from the processing circuits 14 through 16.
FIG. 29(B) of the accompanying drawings shows a detail structure of the reference block 18. As shown in FIG. 29(B), the reference block 18 comprises a reference table 18a and a comparator 18b. 
The reference table 18a is made up of a reference field and a data field. The reference field stores destination MAC addresses, and the data field stores the port numbers of corresponding input/output ports.
The comparator 18b compares a destination MAC address supplied from a requesting one of the processing circuits 14 through 16 with the destination MAC addresses stored in the reference field of the reference table 18a. If there is a matching destination MAC address, then the comparator 18b acquires a corresponding port number as control information from the data field of the reference table 18a, and supplies the acquired port number to the requesting processing circuit.
The CPU 20 changes the header of packets and recalculates CRC (Cyclic Redundancy Check) codes when it performs a routing process.
Operation of the above conventional access router will be described below. It is assumed that the input/output port 11 has a port number #1 and the input/output ports 12, 13 have respective port numbers #2, #3, and that the input/output ports 11, 12 are connected to respective hosts and the input/output port 13 is connected to the WAN.
The host connected to the input/output port 11 transmits a packet toward the host connected to the input/output port 12.
The input/output port 11 receives the packet transmitted from the host and supplies the received packet to the processing circuit 14.
The header information extractor 14c of the processing circuit 14 extracts a destination MAC address from the packet. In this example, the header information extractor 14c acquires the MAC address #2 which is the MAC address of the host connected to the input/output port 12.
The MAC address #2 thus acquired is supplied via the reference block interface 14a to the reference block 18.
The comparator 18b of the reference block 18 compares the acquired MAC address #2 with the MAC addresses stored in the reference field of the reference table 18a. Since the acquired MAC address #2 matches the second item in the reference field, the comparator 18b acquires the corresponding port number #2 and supplies the port number #2 to the requesting processing circuit 14.
The processing circuit 14 acquires the port number #2 via the reference block interface 14a, and supplies the acquired port number #2 together with the packet to the switch block 17 via the switch block interface 14b. 
The switch block 17 temporarily stores the supplied packet in its buffer, and then supplies the packet to the processing circuit 15 corresponding to the identified port number #2.
The switch block interface of the processing circuit 15 receives the packet supplied from the switch block 17, and supplies the received packet to the host via the input/output port 12.
Packets can thus be transferred between hosts according to the above process.
With the conventional access router shown in FIG. 28, the layer 2 switch 10 which is hardware-implemented can process a level of information which literally belongs to the layer 2. In order for the conventional access router to be able to perform other processes involving high-level decision making steps (e.g., a filtering process), the CPU 20 needs to take part in sharing the operation.
The recent increase in the communication rate tends to impose a greater load on the CPU 20. As a result, when the CPU 20 performs a high-level process, the CPU 20 is overloaded and sometimes fails to carry out the process, often losing packets which are to be transferred.
Access routers are desired to reliably keep response times and throughputs required by respective communication sessions for increased QoS (Quality of Service) by assigning optimum frequency bands depending on the purpose of the communication sessions.
In order to achieve a desired level of QoS with a layer 2 switch, it has been customary for the switch to process successive packets based on identifiers indicative of priority which are contained in packet headers in the data link layers according to the IEEE 802.1 p/Q. However, it is difficult to apply a policy of unified application levels because each application manages packet priority with a TOS field in the IP packet header and a port number in the TCP/UDP header when it determines the priority ranking of a packet. These items of information correspond to information of 3rd and 4th layers of an OSI 7-layer model. It depends on the skill of the network administrator to determine how to map these items of information onto the layer 2. Specifically, the network administrator may rank application priorities in a manner not intended by the applications, or may leave application priorities as set by default, so that the application priorities will not be reflected in the 2nd layer (data link layer).
If priorities can be set in the application level based on the information contained in the 3rd and 4th layers, then unified priorities can be set for packets from any terminals where any applications are installed. Specifically, it is possible to specify flow-based priorities based on a combination of destination IP address, source IP address, destination TCP/UDP port number, and source TCP/UDP port number. However, since the conventional layer 2 switch cannot refer to these items of information, the above scheme is not applicable to the conventional layer 2 switch.
If the above functions are to be software-implemented by the CPU, then the CPU is required to process all the packets received from all the interfaces. In reality, however, the CPU does not have a sufficient processing ability to process all the packets received from all the interfaces.